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| document:1g5-0145 rev.1 page 1 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram overview the vg4616321(2) sgram is a high-speed cmos synchronous graphics ram containing 16m bits. it is internally configured as a dual 256k x 32 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 256k x 32 bit banks is organized as 1024 rows by 256 columns by 32 bits. read and write accesses to the sgram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the vg4616321(2) provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with burst termination option. an auto precharge function may be enabled to provide a self-timed row pre- charge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. in addition, it features the write per bit and the masked block write functions. by having a programmable mode register and special mode register, the system can choose the best suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device particularly well suited to high performance graphics applications. features ? fast access time from clock: 4.5/5/5.5ns ? fast clock rate: 200/166/143 mhz ? fully synchronous operation ? internal pipelined architecture ? dual internal banks(256k x 32-bit x 2-bank) ? programmable mode and special mode registers - cas latency: 1, 2, or 3 - burst length: 1, 2, 4, 8, or full page - burst type: interleaved or linear burst - burst read single write - load color or mask register ? burst stop function ? individual byte controlled by dqm0-3 ? block write and write-per-bit capability ? auto refresh and self refresh ? 2048 refresh cycles/32ms ? single + 3.3v power supply ? input reference voltage : vref = 1.5v 0.2v ? interface: lvttl and sstl_3 ? jedec 100-pin plastic qfp package 0.3v
document:1g5-0145 rev.1 page 2 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram key specifications vg4616321/vg4616322 -5/6/7 t ck clock cycle time(min.) 5/6/7 ns t ras row active time(min.) 30/36/40 ns t ac access time from clk(max.) 4.5/5/5.5 ns t rc row cycle time(min.) 45/54/62 ns dq3 1 v ddq 2 dq4 3 dq5 4 v ssq 5 dq6 6 dq7 7 v ddq 8 dq16 9 dq17 10 11 dq18 12 dq19 13 v ddq 14 15 16 17 dq21 18 19 v ssq 20 dq23 21 22 dqm0 23 24 we 25 cas 26 ras 27 cs 28 bs 29 a8 30 dq28 v ddq dq27 dq26 v ssq v ddq dq15 dq14 v ssq dq13 dq12 v ddq v ss dq11 dq10 dq9 dq8 nc/vref dqm3 dqm1 clk cke dsf nc a9 v ssq v dd v ss dq20 dq22 v ddq dqm2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dq24 v dd v ssq v ddq d q 2 9 v s s q d q 3 0 d q 3 1 v s s n c n c n c n c n c n c n c n c n c d q 0 d q 1 d q 2 n c v d d v s s q 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 8 1 a 7 a 6 a 5 a 4 v s s n c n c n c n c n c n c n c n c n c a 3 a 2 a 0 n c v d d a 1 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 5 0 document:1g5-0145 rev.1 page 3 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram cs ras cas we dsf clock buffer command decoder column counter address buffer refresh counter mode register special mode register control signal generator color register mask register column decoder 1024 x 256 x 32 cell array (bank #0) r o w d e c o d e r sense amplifier sense amplifier 1024 x 256 x 32 cell array (bank #1) r o w d e c o d e r column decoder dqs buffer clk cke dqm0~3 dq0 dq31 | a0 a8 ~ bs a9 block diagram document:1g5-0145 rev.1 page 4 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram table 1 shows the details for pin number, symbol, type, and description. table 1. pin description of vg4616321 pin num- ber symbol type description 55 clk input clock: clk is driven by the system clock. all sgram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and con- trol the output registers. 54 cke input clock enable: cke activates(high) and deactivates(low) the clk signal. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when both banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes providing low standby power. 29 bs input bank select: bs defines to which bank the bankactivate, read, write, or bank- precharge command is being applied. bs is also used to program the 10th bit of the mode and special mode registers. 30-34, 47-51 a0-a9 input address inputs: a0-a9 are sampled during the bankactivate command (row address a0-a9) and read/write command (column address a0-a7 with a9 defin- ing auto precharge) to select one location out of the 256k available in the respec- tive bank. during a precharge command, a9 is sampled to determine if both banks are to be precharged (a9 = high). the address inputs also provide the op-code during a mode register set or special mode register set command. 28 cs input chip select: cs enables (sampled low) and disables (sampled high) the com- mand decoder. all commands are masked when cs is sampled high. cs provides for external bank selection on systems with multiple banks. it is considered part of the command code. 27 ras input row address strobe: the ras signal defines the operation commands in con- junction with the cas and we signals, and is latched at the positive edges of clk. when ras and cs are asserted ?low? and cas is asserted ?high?, either the bankactivate command or the precharge command is selected by the we signal. when the we is asserted ?high? the bankactivate command is selected and the bank designated by bs is turned on to the active state. when the we is asserte d "low", the precharge command is selected and the bank designated by bs is switched to the idle state after precharge operation. 26 cas input column address strobe: the cas signal defines the operation commands in conjunction with the ras and we signals, and it is latched at the positive edges of clk. when ras is held ?high? and cs is asserted ?low?, the column access is started by asserting cas ?low?. then, the read or write command is selected by asserting we ?low? or ?high?. 25 we input write enable: the we signal defines the operation commands in conjunction with the ras and cas signals, and it is latched at the positive edges of clk. the we input is used to select the bankactivate or precharge command and read or write command. 53 dsf input define special function: the dsf signal defines the operation commands in conjunction with the ras and cas and we signals, and it is latched at the positive edges of clk. the dsf input is used to select the masked write disable/enable command and block write command, and the special mode register set cycle. document:1g5-0145 rev.1 page 5 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram 23,56,24, 57 dqm0- dqm3 input data input/output mask: dqm0-dqm3 are byte specific, nonpersistent i/o buffer controls. the i/o buffers are placed in a high-z state when dqm is sampled high. input data is masked when dqm is sampled high during a write cycle. output data is masked (two-clock latency) when dqm is sampled high during a read cycle. dqm3 masks dq31-dq24, dqm2 masks dq23-dq16, dqm1 masks dq15-dq8, and dqm0 masks dq7-dq0. 97,98,100, 1,3,4,6,7, 60,61,63, 64,68,69, 71,72,9, 10,12,13, 17,18,20, 21,74,75, 77, 78,80, 81, 83, 84 dq0- dq31 input/ output data i/o: the dq0-31 input and output data are synchronized with the positive edges of clk. the i/os are byte-maskable during reads and writes. the dqs also serve as column/byte mask inputs during block writes. 30,36-45, 52,86-95 nc - no connect: these pins should be left unconnected. 58 nc/vref -/input no connect/input voltage reference : it must be unconnected when the lvttl interface is used in the sgram. it must be applied to vref (1.5v) when the sstl-3 interface is used in the sgram. 2,8,14,22, 59,67,73, 79 v ddq supply dq power: provide isolated power to dqs for improved noise immunity. 5,11,19, 62,70,76, 82,99 v ssq su pply dq ground: provide isolated ground to dqs for improved noise immunity. 15,35,65, 96 v dd supply power supply: +3.3v 16,46,66, 85 v ss supply ground 0.3v document:1g5-0145 rev.1 page 6 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 2 shows the truth table for the operation commands. table 2. truth table (note(1), (2)) note: 1. v = valid x = don?t care l = low level h = high level 2. cke n signal is input level when commands are provided. cken-1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by bs signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. the special mode register set is also available in row active state. 6. power down mode can not entry in the burst operation. when this command assert in the burst cycle, device state is clock suspend mode. 7. dqm0-3 command state cken-1 cken dqm (7) bs a9 a0-8 cs ras cas we dsf bankactivate & masked write disable idle (3) h x x v v v l l h h l bankactivate & masked write enable idle (3) h x x v v v l l h h h bankprecharge any h x x v l x l l h l l prechargeall any h x x x h x l l h l l write active (3) h x x v l v l h l l l block write command active (3) h x x v l v l h l l h write and autoprecharge active (3) h x x v h v l h l l l block write and autoprecharge active (3) h x x v h v l h l l h read active (3) h x x v l v l h l h l read and autoprecharge active (3) h x x v h v l h l h l mode register set idle h x x v l v l l l l l special mode register set idle (5) h x x x x v l l l l h no-operation any h x x x x x l h h h x burst stop active (4) h x x x x x l h h l l device deselect any h x x x x x h x x x x autorefresh idle h h x x x x l l l h l selfrefresh entry idle h l x x x x l l l h l selfrefresh exit idle (selfrefresh) l h x x x x h x x x x l h h h x clock suspend mode entry active h l x x x x x x x x x power down mode entry any (6) h l x x x x h x x x x l h h h l clock suspend mode exit active l h x x x x x x x x x power down mode exit any (power- down) l h x x x x h x x x x l h h h l data write/output enable active h x l x x x x x x x x data write/output disable active h x h x x x x x x x x document:1g5-0145 rev.1 page 7 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram commands 1 bankactivate & masked write disable command ( ras = ?l?, cas = ?h?, we = ?h?, dsf = ?l?, bs = bank, a0-a9 = row address) the bankactivate command activates the idle bank designated by the bs (bank select) signal. by latching the row address on a0 to a9 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t rc (min.). the sgram has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the back-to-back activation of both banks. t rrd (min.) specifies the mini- mum time required between activating different banks. after this command is used, the write command and the block write command perform the no mask write operation. clk address bank a t0 t1 t2 t3 tn+3 tn+4 tn+5 tn+6 row addr. bank a col addr. bank a row addr. bank a row addr. command bank a activate r/w a with autoprecharge bank b activate bank a activate nop nop nop nop autoprecharge begin ras cycle time (t rc ) ras - cas delay (t rcd ) ras - ras delay time (t rrd ) : ?h? or ?l? bankactivate command cycle (burst length = n, cas latency = 3) 2 bankactivate & masked write enable command (refer to the above figure) ( ras = ?l?, cas = ?h?, we = ?h?, dsf = ?h?, bs = bank, a0-a9 = row address) the bankactivate command activates the idle bank designated by bs signal. after this command is performed, the write command and the block write command perform the masked write operation. in the masked write and the masked block write functions, the i/o mask data that was stored in the write mask register is used. 3 bankprecharge command ( ras = ?l?, cas = ?h?, we = ?l?, dsf = ?l?, bs = bank, a9 = ?l?, a0-a8 = don?t care) the bankprecharge command precharges the bank designated by bs signal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still the idle state and ready to be activated again. 4 prechargeall command ( ras = ?l?, cas = ?h?, we = ?l?, dsf = ?l?, bs = don?t care, a9 = ?h?, a0-a8 = don?t care) the prechargeall command precharges both banks simultaneously. even if both banks are not in the active state, the prechargeall command can be issued. both banks are then switched to the idle state. 5 read command ( ras = ?h?, cas = ?l?, we = ?h?, dsf = ?l?, bs = bank, a9 = ?l?, a0-a7 = column address, a8 = don?t care) document:1g5-0145 rev.1 page 8 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram the read command is used to read burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before read command is issued. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the issue of read command. each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). the dqs goes into high-imped- ance at the end of the burst, unless other command was initiated. the burst length, burst sequence, and cas latency are determined by the mode register which is already prgrammed.a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command read a t0 t1 t2 t3 cas iatency = 1 t4 t5 t6 t7 t8 nop t ck1 ,dq?s nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 burst read operation (burst length = 4, cas latency = 1, 2, 3) cas iatency = 2 t ck2 ,dq?s cas iatency = 3 t ck3 ,dq?s the read data appears on the dqs subjects to the values on the dqm inputs two clocks early (i.e. dqm latency is two clocks for output buffers). a read burst without auto precharge function may be interrupted by a subsequent read or write/block write command to the same bank or the other active bank before the end of burst length. it may be interrupted by a bankprecharge/prechargeall command to the same bank too. the interrupt comes from read command can occur on any clock cycle following a previous read command (refer to the following figure). t0 t1 t2 t3 t4 t5 t6 t7 t8 clk command read a cas iatency = 1 read b t ck1 ,dq?s nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout a 0 dout b 0 dout b 1 dout b 2 dout a 0 dout b 0 dout b 1 dout b 2 read interrupted by a read (burst length = 4, cas latency = 1, 2, 3) cas iatency = 2 t ck2 ,dq?s cas iatency = 3 t ck3 ,dq?s dout b 3 dout b 3 dout b 3 the dqm inputs are used to avoid i/o contention on dq pins when the interrupt comes from write/block write command. the dqms must be asserted (high) at least two clocks prior to the write/block write command to suppress data-out on dq pins. to guarantee dq pins against the i/o contention, a single cycle with high-impedance on dq pins must occur between the last read data and the write/block write command (refer to the following three figures). if the data output of burst read occurs at the second clock of burst write, the dqms must be asserted (high) at least one clock prior to the write/block write command to avoid internal bus contention. document:1g5-0145 rev.1 page 9 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t0 t1 t2 t3 t4 t5 t6 t7 t8 t0 t1 t2 t3 t4 t5 t6 t7 t8 clk command nop read a nop nop nop nop write b nop nop read to write interval (burst length ? 4, cas latency = 3) dqm dout a 0 dq?s dinb 0 dinb 1 dinb 2 : ?h? or ?l? must be hi-z before the write command clk command nop nop bank a nop read a write a nop nop nop read to write interval (burst length ? 4, cas latency = 1, 2 ) dqm din a 0 din a 1 din a 2 din a 3 : ?h? or ?l? must be hi-z before the write command din a 0 din a 1 din a 2 din a 3 cas iatency = 1 t ck1 ,dq?s cas iatency = 2 t ck2 ,dq?s activate clk command nop nop nop write b nop nop nop read to write interval (burst length ? 4, cas latency = 1, 2 ) dqm din b 0 din b 1 dinb 2 din b 3 : ?h? or ?l? must be hi-z before the write command din b 0 din b 1 din b 2 din b 3 cas iatency = 1 t ck1 ,dq?s cas iatency = 2 t ck2 ,dq?s read a dout a 0 nop a read burst without auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bankprecharge/prechargeall command is issued in different cas latency. 1 clk interval document:1g5-0145 rev.1 page 10 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 clk address dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 cas iatency = 1 t ck1 ,dq?s cas iatency = 2 t ck2 ,dq?s bank bank(s) dout a 0 dout a 1 dout a 2 dout a 3 command read a nop nop precharge nop nop nop cas iatency = 3 t ck3 ,dq?s col a bank row nop activate 6 read and autoprecharge command ( ras = ?h?, cas = ?l?, we = ?h?, dsf = ?l?, bs = bank, a9 = ?h?, a0-a7 = column address, a8 = don?t care ) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subsequent command can not occur within a time delay of {t rp (min.) + burst length}. at full-page burst, only read operation is performed in this command and the auto pre- charge function is ignored. 7 write command ( ras = ?h?, cas = ?l?, we = ?l?, dsf = ?l?, bs = bank, a9 = ?l?, a0-a7 = column address, a8 = don?t care ) the write command is used to write burst of data on consecutive clock cycles from an active row in an active bank. t he bank must be active for at least t rcd (min.) before write command is issued. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data ele- ments will be registered on each successive positive clock edge (refer to the following figure). the dqs remains high-impedance at the end of the burst, unless other command was initiated. the burst length and burst sequence are determined by the mode register which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). t rp read to precharge ( cas latency = 1, 2, 3 ) clk command nop dq0 - dq3 din a 0 nop write a nop nop nop nop nop nop din a 1 din a 3 din a 2 don?t care the first data element and the write t0 t1 t2 t3 t4 t5 t6 t7 t8 are registered on the same clock edge. extra data is masked. burst write operation (burst length = 4, cas latency = 1, 2, 3) any write performed to a row that was opened via an bankacitvate & masked write enable command is a masked write (write-per-bit). data is written to the 32 cells (bits) at the selected column location subject to the data stored in the mask register. the overall mask consists of the dqm inputs, which mask on a per-byte basis, and the mask register, which masks on a per-bit basis. this is shown in the following block diagram. document:1g5-0145 rev.1 page 11 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram q dsf bankactivate command mr7 mr6 mr5 mr4 mr3 mr1 mr0 mr2 d ck dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 cell dram 0 = masked note: only lower byte is shown. the operation is identical for other bytes. write per bit (i/o mask) block diagram a write burst without auto precharge function may be interrupted by a subsequent write/block write, bankprecharge/prechargeall, or read command before the end of burst length. the interrupt comes from write/block write command can occur on any clock cycle following the previous write command ( refer to the following figure). dqm0 t0 t1 t2 t3 t4 t5 t6 t7 t8 clk command nop write a write b nop nop nop nop nop nop din b 2 write interrupted by a write (burst length = 4, cas latency = 1, 2, 3) din b 3 1 clk interval din a 0 din b 0 din b 1 dq?s the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge at which the last data-in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs will be ignored, and writes will not be executed. 1 = not masked document:1g5-0145 rev.1 page 12 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 clk command write a nop nop nop nop read b nop nop nop din a 0 din a 0 din a 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 cas latency = 1 t ck1 ,dq?s cas latency = 2 t ck3 ,dq?s cas latency = 3 t ck2 ,dq?s don?t care don?t care don?t care input data for the write is masked input data must be removed from dq? s at least one clock cycle before the read data appears on the outputs to avoid data contention write interrupted by a read (burst length = 4, cas latency = 1, 2, 3) the bankprecharge/prechargeall command that interrupts a write burst without auto pre- charge function should be issued m cycles after the clock edge at which the last data-in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the bankprecharge/prechargeall com- mand is entered (refer to the following figure). nop clk dq dqm write nop nop nop precharge activate command bank coln bank (s) row din n din n+1 t rp address :don?t care write to precharge t wr when burst-read and single-write mode is selected , the write burst length is 1 regardless of the read burst length (refer to figures 21 and 22 in timing waveforms). 8 block write command ( ras = ?h? , cas = ?l? , we = ?l?, dsf = ?h? , bs =bank , a9 = ?l? , a3-a7 = column address, dq0-dq31 = column mask) the block writes are non-burst accesses that write to eight column locations simultaneously. a single data value, which was previously loaded in the color register, is written to the block of eight consecutive col- umn locations addressed by inputs a3-a7. the information on the dqs which is registered coincident with the block write command is used to mask specific column/byte combinations within the block . the mapping of the dq inputs to the column/byte combinations is shown in following table. t0 t1 t2 t3 t4 t5 t6 dout b 0 document:1g5-0145 rev.1 page 13 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram dq inputs column address dq planes controlled dq inputs column address dq planes controlled a2 a1 a0 a2 a1 a0 dq0 0 0 0 0~7 dq16 0 0 0 16~23 dq1 0 0 1 0~7 dq17 0 0 1 16~23 dq2 0 1 0 0~7 dq18 0 1 0 16~23 dq3 0 1 1 0~7 dq19 0 1 1 16~23 dq4 1 0 0 0~7 dq20 1 0 0 16~23 dq5 1 0 1 0~7 dq21 1 0 1 16~23 dq6 1 1 0 0~7 dq22 1 1 0 16~23 dq7 1 1 1 0~7 dq23 1 1 1 16~23 dq8 0 0 0 8~15 dq24 0 0 0 24~31 dq9 0 0 1 8~15 dq25 0 0 1 24~31 dq10 0 1 0 8~15 dq26 0 1 0 24~31 dq11 0 1 1 8~15 dq27 0 1 1 24~31 dq12 1 0 0 8~15 dq28 1 0 0 24~31 dq13 1 0 1 8~15 dq29 1 0 1 24~31 dq14 1 1 0 8~15 dq30 1 1 0 24~31 dq15 1 1 1 8~15 dq31 1 1 1 24~31 the overall block write mask consists of a combination of the dqm inputs, the mask register, and the column/byte mask information, as shown in the following diagram. the dqm and mask reg- ister masking operates as for normal write command, with the exception that the mask information is applied simultaneously to all eight columns. therefore, in a block write, a given bit is written only if a ?0? was registered for the corresponding dqm input, a ?1? was registered for the corresponding dq signal, and the corresponding bit in the mask register is ?1?. a block write access requires a time period of t bwc to execute, so in general, there should be m nop cycles, m equals (t bwc -t ck ) /t ck rounded up to the next whole number, after the block write command. however, bankactivate or bankprecharge commands to the other bank are allowed. when following a block write with a bankprecharge or prechargeall command to the same bank, t bpl must be met. document:1g5-0145 rev.1 page 14 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram block of columns (selected by a3-a7 registered coincident with block write command) row in bank (selected by a0-a9, and bs registered coincident with bankactivate command) column mask on the dq inputs (registered coincident with block write command dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmo d q ck dsf bankactivate command mr0 note: only lower byte is shown. the operation is identical for other bytes. block-write masking block diagram mr1 mr2 mr3 mr4 mr5 mr6 mr7 mask register (previously loaded from corresponding dq inputs c r 0 c r 1 c r 2 c r 3 c r 4 c r 5 c r 6 c r 7 document:1g5-0145 rev.1 page 15 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t ck2 ,dq?s 10 block write and autoprecharge command ( ras = ?h? , cas = ?l? , we = ?h?, dsf = ?h? , bs = bank , a9 = ?h? , a3-a7 = column address, a8 = don?t care dq0-dq31 = column mask) the block write and autoprecharge command performs the precharge operation automatically after the block write operation. once this command is given, any subsequent command can not occur within a time delay of {t bpl + t rp (min.)}. 11 mode register set command ( ras = ?l? , cas = ?l?, we = ?l? , dsf = ?l? , bs , a0-a9 = register data) the mode register stores the data for controlling the various operating modes of sgram. the mode register set command programs the values of cas latency. addressing mode and burst length in the mode register to make sgram useful for variety of different applications. the default values of the mode register after power-up are undefined, therefore this command must be issued at the power-up sequence. the state of pins a0-a9 and bs in the same cycle is the data written in the mode register. one clock cycle is required to complete the write in the mode register (refer to the following figure ). the mode register contents can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state. nop t0 t1 t2 t3 t4 t5 t6 clk nop nop command cas latency = 1 t7 t8 nop nop nop write a auto precharge nop bank a activate din a 0 din a 1 din a 0 din a 1 din a 0 din a 1 t dal t dal t dal * * * * cas latency = 2 t dal = t wr + t rp begin autoprecharge bank can be reactivated at completion of t dal burst write with auto-precharge (burst length = 2, cas latency = 1, 2, 3) 9 write and autoprecharge command (refer to the following figure) ( ras = ?h? , cas = ?l? , we = ?l? , dsf=?l? , bs = bank, a9 = ?h?, a0-a7 = column address, a8 = don?t care ) the write and autoprecharge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of {burst length + t wr + t rp (min.)}. at full-page burst, only write operation is performed in this command and the auto precharge function is ignored. t ck1 ,dq?s cas latency = 3 t ck3 ,dq?s document:1g5-0145 rev.1 page 16 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t10 t9 t ck 2 clock min cke clk cs ras cas we dsf bs a9 a0-a8 dqm dq address key hi-z t rp prechargeall mode register set command any command the mode register is divided into various fields depending on functionality. ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 1, 2, 4, 8, or full page. a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page mode register set cycle ( cas latency = 1, 2, 3) document:1g5-0145 rev.1 page 17 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram ? addressing mode select field (a3) the addressing mode can be one of two modes, interleave mode or sequential mode. sequential mode supports burst length of 1, 2, 4, 8, or full page. but, lnterleave mode only supports burst length of 4 and 8. --- addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device. the internal column address is varied by the burst length as shown in the following table. when the value of column address, (n+m), in the table is larger than 255, only the least significant 8 bits are effective. --- addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bits in the sequence shown in following table. ? cas latency field (a6 ~ a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum value of cas latency depends on the frequency of clk. and this value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck a3 addressing mode 0 sequential 1 interleave data n 0 1 2 3 4 5 6 7 - 255 256 257 - column address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - burst length data n column address burst length data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a7 a6 a5 a4 a3 a2 a1 a0 data 3 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a7 a6 a5 a4 a3 a2 a1 a0 data 5 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a7 a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 clock 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved 2 words: 4 words : 8 words: full page: column address is repeated until terminated. 4 words 8 words document:1g5-0145 rev.1 page 18 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram ? mode field (a8~a7) a7 and a8 must be programmed to ?00? in normal operation. a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only ? single write mode (a9) this bit is used to select the write mode. when the a9 bit is ?0?, burst read and burst write mode is selected. when the a9 bit is ?1?, burst read and single write mode is selected. a9 single write mode 0 burst read and burst write 1 burst read and single write 12 special mode register set command ( ras = ?l?, cas = ?l?, we = ?l?, dsf = ?h?, bs, a0-a9 = register data) the special mode register is used to load the color and mask registers, which are used in block write and masked write cycles. the control information being written to the special mode register is applied to the address inputs and the data to be written to either the color register or the mask register is applied to the dqs. when a6 is ?high? during a special mode register set cycle, the color register will be loaded with the data on the dqs. similarly, when a5 is ?high? during a special mode register set cycle, the mask register will be loaded with the data on the dqs. a6 = a5 = 1 in the special mode register set cycle is illegal. on e clock cycle is required to complete the write in the special mode register. this command can be issued at the active state. as in write operation, this command accepts the data needed through dq pins. therefore it should be attended not to induce bus contention. 13 no-operation command ( ras = ?h?, cas = ?h?, we = ?h?) the no-operation command is used to perform a nop to sgram which is selected ( cs is low). this prevents unwanted commands from being registered during idle or wait states. 14 burst stop command ( ras = ?h?, cas = ?h?, we = ?l?, dsf = ?l?) burst stop command is used to terminate either fixed-length or full-page bursts. this command is only effective in a read/write burst without auto precharge function. the terminated read burst ends after a delay equal to the cas latency (refer to the following figure). the termination of a write burst is shown in the following figure. functions bs a9~a7 a6 a5 a4~a0 leave unchanged x x 0 0 x load mask register x x 0 1 x load color register x x 1 0 x illegal x x 1 1 x document:1g5-0145 rev.1 page 19 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 clk command read a cas iatency = 1 nop t ck1 ,dq?s nop nop burst stop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 t ermi n ation of a burst write operation (burst length > 4, cas latency = 1, 2, 3) cas iatency = 2 t ck2 ,dq?s cas iatency = 3 t ck3 ,dq?s the burst ends after a delay equal to the cas latency. clk command burst stop cas latency = 1, 2, 3 nop write a nop nop nop nop nop nop din a 0 din a 2 din a 1 don?t care t0 t1 t2 t3 t4 t5 t6 t7 t8 input data for the write is masked. termination of a burst write operation (burst length = x, cas latency = 1, 2, 3) dq?s 15 device deselect command ( cs = ?h?) the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored, regardless of whether the clk is enabled. this command is sim- ilar to the no operation command. 16 autorefresh command (refer to figures 3 & 4 in timing waveforms) ( ras = ?l?, cas = ?l?, we = ?h?, dsf = ?l?, cke = ?h?, bs, a0-a9 = don?t care) the autorefresh command is used during normal operation of the sgram and is anala- gous to cas -before- ras (cbr) refresh in conventional drams. this command is non-persis- tent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an autorefresh command. the internal refresh counter increments automatically on every auto refresh cycle to all of the rows. the refresh operation must be performed 2048 times within 32ms. the time required to complete the auto refresh operation is specified by t rp (min.). to provide the autore- fresh command, both banks need to be in the idle state and the device is not in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operations is completed. the precharge time requirement, t rp (min.). must be met befor successive auto refresh operations are performed. 17 selfrefresh entry command (refer to figure 5 in timing waveforms) ( ras = ?l?, cas = ?l?, we = ?h?, dsf = ?l?, cke = ?l?, bs, a0-a9 = don?t care) the selfrefresh is another refresh mode available in the sgram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the inputs to the sgram becomes ?don?t care? with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power comsumption. the sgram may remain in selfrefresh mode for an indefinite period. once the sgram enters the selfrefresh mode , t ras (min.) is required before exit from selfrefresh mode. the selfre- fresh mode is exited by restarting the external clock and then asserting high on cke(selfrefresh exit command). document:1g5-0145 rev.1 page 20 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram 18 selfrefresh exit command (refer to figure 5 in timing waveforms) (cke = ?h?, cs = ?h? or cke = ?h?, ras = ?h?, cas = ?h?, we = ?h?) the command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for t rc (min), because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are per- formed during normal operation, a burst of 1024 auto refresh cycles should be completed just prior to entering, and just after exiting the selfrefresh mode. 19 clock suspend mode entry/powerdown mode entry command (refer to figures 6, 7, and 8 in timing waveforms) (cke = ?l?) when sgram operating the burst cycle, the internal clk is suspended (masked) from the sub- sequent cycle by issuing this command (asserting cke ?low?). the device operation is held intact while clk is suspended. on the other hand, when both banks are in the idle state, this command per- forms entry into the powerdown mode. all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (16ms) since the command does not perform any refresh operations. 20 clock suspend mode exit/powerdown mode exit command (refer to figures 6, 7, and 8 in timing waveforms) (cke = ?h?) when the internal clk has been suspended, the operation of the internal clk is resumed from the subsequent cycle by providing this command (asserting cke ?high?). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exit from the powerdown mode. any subsequent com- mands can be issued after one clock cycle from the end of this command. 21 data write/output enable, data mask/output disable command (dqm = ?l?, ?h?) during a write cycle, the dqm signal functions as data mask and can control every word of the input data. during a read cycle, the dqm functions as the control of output buffers. dqm is also used for device selection, byte selection and bus control in a memory system. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 controls dq16 to dq23, dqm3 controls dq24 to dq31, dqm masks the dq?s by a byte regardless that the corresponding dq?s are in a state of write-per-bit mask- ing or pixel masking. the byte control. the each dqm0-3 corresponds to dq0-7, dq8-15, dq16-23, dq24-31. document:1g5-0145 rev.1 page 21 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram absolute maximum rating symbol item rating unit note v in , v out input, output voltage -0.3~vdd + 0.3 v 1 v dd , v ddq power supply voltage -0.3~4.6 v 1 t opr operating temperature 0~70 c 1 t stg storage temperature -55~150 c 1 t solder soldering temperature(10s) 260 c 1 p d power dissipation 1 w 1 i out short circuit output current 50 ma 1 recommended d.c. operating conditions (ta = 0~70c ) note : the peak to peak ac noise on vref may not exceed 2%. v ref (dc). vtt of transmitting device must track v ref of receiving device. typically the value of v ref must be about 0.45 * v ddq of the transmitting device and v ref track variations in v ddq . capacitance (vdd = 3.3v, f = 1 mhz, ta = 25c ) note: these parameters are periodically sampled and are not 100% tested. symbol parameter min. typ. max. unit note v dd power supply voltage 3.0 3.3 3.6 v 2 v ddq power supply voltage (for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 - v dd + 0.3 v 2 v il lvttl input low voltage -0.3 - 0.8 v 2 v ref input reference voltage 1.25 1.5 1.75 v 2 v ih sstl input high voltage v ref +0.2 - v ddq +0.3 v 2 v il sstl input low voltage -0.3 - v ref +0.2 v 2 v tt sstk teruination voltage v ref -0.1 v v ref +0.1 v 2 symbol parameter min. max. unit c i input capacitance - 5 pf c i/o input/output capacitance - 7 pf document:1g5-0145 rev.1 page 22 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram recommended d.c. operating conditions (v dd = 3.3v 0.3v, ta = 0 ~ 70 j) description/test condition symbol -5 -6 -7 unit note min . max . min . max . min . max. operating current , outputs open address changed once during t ck(min) . burst length = 1 1 bank operation i dd1 190 170 150 ma 3,4 precharge standby current in non-power down mode t ck = t ck(min) , (min) , (min) input signals are changed once during 30ns. i dd2n 35 35 35 3 precharge standby current in non-power down mode t ck = , (min) , (max) input signals are stable i dd2ns 15 15 15 precharge standby current in power down mode t ck = t ck (min), (max) i dd2p 2.0 2.0 2.0 3 precharge standby current in power down mode t ck = , (max) , (max) i dd2ps 2.0 2.0 2.0 active standby current in non power down mode (min) , t ck = t ck(min) i dd3p 4 4 4 3 active standby current in power down mode (max) , t ck = t ck(min) , cs v ih(min) i dd3n 30 30 30 operating current (page burst, and all bank activated) t ccd = t ccd(min) , outputs open, multi-bank interleave, gapless data i dd4 220 200 170 4,5 refresh current (min) i dd5 190 170 140 3 self refresh current i dd6 1 1 1 operating current (block write) t ck = t ck(min) , outputs open, t bwc = t bwc(min) i dd7 250 230 190 parameter description min. max. unit note i il input leakage current ( all other pins not under test = ov) -5 5 a i ol output leakage current output disable, ( ) -5 5 a v oh lvttl output ?h? level voltage (l out = -2ma) 2.4 - v v ol lvttl output ?l? level voltage (l out = 2ma) - 0.4 v v oh sstl output ?h? level voltage (l out = -16ma) v tt +0.8 - v v ol sstl output ?l? level voltage (l out = 16ma) - v tt +0.8 v t r c t r c mi n ( ) 3 c s v i h 3 ck e v i h 3 ck e v i h 3 cl k v i l ck e v i l ck e v i l cl k v i l ck e v i h 3 ck e v i l 3 t r c t r c 3 ck e 0.2 v 0 v v i n v d d m 0 v v ou t v dd q m document:1g5-0145 rev.1 page 23 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram electrical characteristics and recommended a.c. operating conditions (v dd = 3.3v0.3v, ta = 0~70c) (note: 6, 7, 8, 9, 10) *** cl is cas latency. symbol a.c. parameter -5 -6 -7 unit min. max. min. max. min. max. t rc row cycle time 45 54 62 ns t rcd ras to cas delay 15 18 20 t rp precharge to refresh/row activate com- mand 15 18 20 t rrd row activate to row activate delay 10 12 14 t ras row activate to precharge time 30 100,000 36 100,000 40 100,000 t wr write recovery time 1 1 1 clk t ck1 clock cycle time cl* = 1 14 16 18 ns t ck2 7 8 9 t ck3 5 6 7 t ch clock high time 1.5 2 2.5 t cl clock low time 1.5 2 2.5 t ac1 access time from clk (positive edge) cl* = 1 11 13 15 t ac2 cl* = 2 5 5 6 t ac3 cl* = 3 4.5 5 5.5 t t transition time of clk (rise and fall) 0.5 10 0.5 10 0.5 10 t ccd cas to cas delay time 1 1 1 clk t oh data output hold time 2 2.5 2.5 ns t lz data output low impedance 2 2 2 t hz1 data output high impedance cl = 1 3 5 3 5 3 6 t hz2 cl = 2 3 5 3 5 3 6 t hz3 cl = 3 3 5 3 5 3 5 t is data/address/control input setup time 1 1 1.5 t ih data/address/control input hold time 1 1 1 t srx minimum cke ?high?for self-refresh exit 1 1 1 clk t pde power down exit set-up time 3 4 5 ns t rsc (special) mode register set cycle time 2 2 2 clk t bwc block write cycle time 1 1 1 clk t dal2 data-in to act command (cl = 2) 1clk +t rp 1clk+ t rp 1clk +t rp t dal3 (cl = 3) 1clk +t rp 1clk+ t rp 1clk +t rp t bpl block write to precharge command 1 1 1 clk t ref refresh time 32 32 32 ms document:1g5-0145 rev.1 page 24 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . assume that there are only one read/write cycle during t rc (min). 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. assume minimum column address update cycle t ccd (min). 6. power-up sequence is described in note 11. 7. a.c. test conditions reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 3.0v / 0.0v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 3.3v 1.2k 870 30pf output lvttl d.c. test load (a) 1.4v 50 30pf output zo=50 lvttl a.c. test load (b) w w w w document:1g5-0145 rev.1 page 25 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram sstl_3 interface reference level of output signals (vref) 0.45*vddq output load reference to the under output load input signal levels v ref + 0.4/v ref -0.4 transition time (rise and fall) of input signals 1ns reference level of input signals(v ref ) 0.45*v ddq v ddq v ref v out device under test v ddq 0.45 * v ddq rs = 25 ohms rt1 = 50 ohms v tt = 0.45 * v ddq v ref = 0.45 * v dd v tt = 0.45 * v ddq rt2 = 50 ohms c load = 30 pf z = 50 ohms v in v ss ac test load circuits (for sstl - 3 interface) : 8. transition times are measured between v ih and v il . transition (rise and fall) of input signals are fixed slope (1 ns). 9. t ohz defines the time at which the outputs achieve the open circuit condition and are not reference levels. 10. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock cycle time (count fractions as a whole number) sstl-3 a.c. test load document:1g5-0145 rev.1 page 26 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram latency relationship to frequency (unit : clock cycles) -5 version (calculation with t ck = 5ns ~ 30ns) -6 version (calculation with t ck = 6ns ~ 30ns) -7 version (calculation with t ck = 7ns ~ 30ns) 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held ?nop? state and cke = ?h?, dqm = ?h?. the clk signals must be started at the same time. 2) after power-up, a pause of 200u secouds minimum is required. then, it is recommended that dqm is held ?high? (v dd levels) to ensure dq output to be in the high impedance. 3) both banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 8 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. sequence of 4 and 5 may be changed. clock period (t ck ) t rc t rp t rrd t ras t rsc t rcd 45 15 10 30 10 15 30ns 2 1 1 1 1 1 20ns 3 1 1 2 1 1 15ns 3 1 1 2 1 1 10ns 5 2 1 3 1 2 5ns 9 3 2 6 2 3 clock period (t ck ) t rc t rp t rrd t ras t rsc t rcd 54 18 12 36 12 18 30ns 2 1 1 2 1 1 20ns 3 1 1 2 1 1 15ns 4 2 1 3 1 2 10ns 6 2 2 4 2 2 6ns 9 3 2 6 2 3 clock period (t ck ) t rc t rp t rrd t ras t rsc t rcd 62 20 12 36 14 20 30ns 3 1 1 2 1 1 20ns 4 1 1 2 1 1 15ns 5 2 1 3 1 2 10ns 7 2 2 4 2 2 7ns 9 3 2 6 2 3 document:1g5-0145 rev.1 page 27 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 timing waveforms clk cke cs ras c as we bs a9 a0 ~ a8 dqm dq t ck2 activate bank a command write with hi-z write precharge auto precharge command rbx cax rbx cbx cay raz ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 command activate command bank b write with auto precharge command activate command bank a bank a command bank a figure 1. ac parameters for write timing (burst length = 4, cas latency = 2) dsf rax ray rby rbx ray raz rby t ch t cl t is t is t ih begin auto precharge bank a begin auto precharge bank b t is t ih t is t rcd t rc t dal t is t ih t wr t rp t rrd bank a bank b activate command bank a activate command bank b document:1g5-0145 rev.1 page 28 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 figure 2. ac parameters for read timing (burst length = 2, cas latency = 2) clk cke bs a9 a0 ~ a8 dqm dq t ch t cl t ck2 begin auto precharge bank b t ih t is t is t ih t ih t is rax rbx ray ray cbx rbx cax rax t rrd t ras t rc t rcd t ac2 t lz t oh t ac2 t hz t rp hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a ax0 bx0 bx1 dsf command cs ras c as we ax1 document:1g5-0145 rev.1 page 29 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 3. auto refresh (cbr) (burst length = 4, cas latency = 2) clk bs a9 a0 ~ a8 dqm dq precharge all command auto refresh command auto refresh command hi-z ax0 rax activate bank a command dsf rax ax1 ax2 ax3 cax read bank a command t rp t rc t rc t ck2 cke cs ras c as we document:1g5-0145 rev.1 page 30 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq inputs must be stable for 200 us precharge all command 2nd auto refresh command hi-z mode register set command t rp t rc 1st auto refresh command any command address key 2 clock min. minimum of 8 refresh cycles are required high level is required t ck2 cke cs ras c as we dsf figure 4. power on sequence and auto refresh (cbr) document:1g5-0145 rev.1 page 31 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 figure 5. self refresh entry & exit cycle clk cke cs ras c as bs a0 ~ a9 we dsf dqm hi-z t is dq self refresh enter hi-z auto refresh self refresh exit * note 1 * note 2 * note 4 t srx * note 5 t pde * note 7 t rc(min) * note 6 * note 8 * note 8 * note 3 note: to enter selfrefresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don?t care except for cke. 3. the device remains in selfrefresh mode as long as cke stays ?low?. once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. note: to exit selfrefresh mode 4. system clock restart and be stable before returning cke high. 5. enable cke and cke should be set high for minimum time of t srx . 6 . cs starts from high. 7. minimum t rc is required after cke going high to complete selfrefresh exit. 8. 1024 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh. document:1g5-0145 rev.1 page 32 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 6.1 clock suspension during burst read (using cke) (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck1 bs rax rax cax ax0 bank a read command bank a clock suspend 2 cycles clock suspend 3 cycles ax1 ax2 ax3 t hz note: cke to clk disable/enable = 1 clock document:1g5-0145 rev.1 page 33 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 6.2 clock suspension during burst read (using cke) (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck2 dsf rax rax cax ax0 bank a read command bank a clock suspend 2 cycles clock suspend 3 cycles ax1 ax2 ax3 t hz note: cke to clk disable/enables = 1 clock document:1g5-0145 rev.1 page 34 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 6.3 clock suspension during burst read (using cke) (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck3 dsf rax rax cax ax0 bank a read command bank a clock suspend 2 cycles clock suspend 3 cycles ax1 ax2 ax3 t hz note: cke to clk disable/enable = 1 clock cke cs ras c as we document:1g5-0145 rev.1 page 35 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 7.1 clock suspension during burst write (using cke) (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck1 dsf rax rax cax dax0 bank a write command bank a clock suspend 2 cycles clock suspend 3 cycles note: cke to clk disable/enable = 1 clock dax1 dax2 dax3 cke cs ras c as we document:1g5-0145 rev.1 page 36 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 7.2 clock suspension during burst write (using cke) (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck2 dsf rax rax cax dax0 bank a write command bank a clock suspend 2 cycles clock suspend 3 cycles note: cke to clk disable/enable = 1 clock dax1 dax2 dax3 cke cs ras c as we document:1g5-0145 rev.1 page 37 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 7.3 clock suspension during burst write (using cke) (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command clock suspend 1 cycle hi-z t ck3 dsf rax rax cax dax0 bank a write command bank a clock suspend 2 cycles clock suspend 3 cycles note: cke to clk disable/enable = 1 clock dax1 dax2 dax3 cke cs ras c as we document:1g5-0145 rev.1 page 38 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 8. power down mode and clock mask (burst length = 4, cas burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk a9 a0 ~ a8 dqm dq activate command power down hi-z t ck2 bs rax rax cax ax0 bank a power down mode entry read clock mask ax3 ax1 t is t pde valid ax2 thz active standby mode exit command bank a start clock mask end precharge command bank a power down mode entry precharge standby power down mode exit any command cke cs ras c as we dsf document:1g5-0145 rev.1 page 39 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 9.1 random column read (page within same bank) (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck1 dsf bank a read command bank a read raw raw caw raz caz cax cay ay2 ay3 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az2 az0 az1 az3 aw0 command bank a read command bank a precharge command bank a activate command bank a read command bank a raz cke cs ras c as we document:1g5-0145 rev.1 page 40 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 9.2 random column read (page within same bank) (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a 8 dqm dq activate command hi-z t ck2 dsf bank a read command bank a read raw raz caz cax cay az2 az0 az1 az3 command bank a read command bank a precharge command bank a read command bank a caw ay2 ay3 aw1 aw2 aw3 ax0 ax1 ay0 ay1 aw0 raw activate command bank a raz cke cs ras c as we document:1g5-0145 rev.1 page 41 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 9.3 random column read (page within same bank) (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck3 dsf bank a read command bank a read note: cke to clk disable/enable = 1 clock command bank a read command bank a precharge command bank a read command bank a ay2 ay3 aw1 aw2 aw3 ax0 ax1 ay0 ay1 aw0 activate command bank a raw raw caw cax cay raz raz caz az0 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 cke cs ras c as we document:1g5-0145 rev.1 page 42 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 10.1 (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck1 dsf bank b command bank b precharge command bank b write command bank b dbw0 random column write (page within same bank) write command bank b write command bank b rbw rbw cbw cbx cby rbz rbz cbz dbw1 dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby2 dby3 dbz0 dbz1 dbz2 dbz3 write activate command bank b cke cs ras c as we document:1g5-0145 rev.1 page 43 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 10.2 (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck2 dsf bank b command bank b precharge command bank b write command bank b dbw0 random column write (page within same bank) write command bank b write command bank b rbw rbw cby cbx cby rbz rbz dbw1 dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby2 dby3 dbz0 dbz1 dbz2 dbz3 write activate command bank b cke cs ras c as we cbz document:1g5-0145 rev.1 page 44 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 10.3 (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck3 dsf bank b command bank b precharge command bank b write command bank b dbw0 random column write (page within same bank) write command bank b write command bank b rbw rbw cbw cbx cby rbz cbz dbw1 dbw2 dbw3 dbx0 dby0 dby1 dby2 dby3 dbz0 dbz1 dbz2 write activate command bank b rbz dbx1 cke cs ras c as we document:1g5-0145 rev.1 page 45 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 11.1 (burst length = 8, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck1 dsf bank b precharge command bank a random row read (interleaving banks) rbx rbx cbx cax rby cby rbx rby rax t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by2 ax7 read command bank b activate command bank a read command bank a precharge command bank b read command bank b activate command bank b t ac1 high cke cs ras c as we t rcd document:1g5-0145 rev.1 page 46 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 11.2 (burst length = 8, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck2 dsf bank b random row read (lnterleaving banks) rbx rbx cbx cax rby cby rbx rby rax bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 ax7 read command bank b activate command bank a read command bank a precharge command bank b read command bank b activate command bank b high cke cs ras c as we t rp t ac2 t rcd document:1g5-0145 rev.1 page 47 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 11.3 (burst length = 8, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck3 dsf bank b random row read (interleaving banks) rbx rbx cbx cax rby cby rax rby rax bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 ax7 read command bank b activate command bank a read command bank a precharge command bank b read command bank b activate command bank b high precharge command bank a cke cs ras c as we t rp t ac3 t rcd document:1g5-0145 rev.1 page 48 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 12.1 (burst length = 8, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs a9 a0 ~ a8 dqm dq activate command hi-z t ck1 dsf bank a random row read (interleaving banks) rax rax cax cbx ray cay rbx ray rbx dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 dbx2 dbx3 dbx4 dbx5 dbx6 dbx7 activate command bank b precharge command bank a activate command bank a high day0 day1 day2 day3 write command bank a write command bank b precharge command bank b write command bank a cke cs ras c as we t rp t wr t rcd document:1g5-0145 rev.1 page 49 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 12.2 (brust length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck2 dsf bank a random row write (interleaving banks) rax rax cax cbx ray cay rbx ray rbx dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 dbx2 dbx3 dbx4 dbx5 dbx6 dbx7 activate command bank b precharge command bank a activate command bank a high day0 day1 day2 day3 write command bank a write command bank b precharge command bank b write command bank a day4 a9 a0 ~ a8 cke cs ras c as we * t wr > t wr(min.) t wr* t wr* t rcd t rp document:1g5-0145 rev.1 page 50 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 12.3 (burst length = 8, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck3 bs bank a random row write (interleaving banks) rbx rbx cax cbx ray cay rbx ray rbx t rp activate command bank b precharge command bank a activate command bank a high t rcd r* t w write command bank a write command bank b precharge command bank b write command bank a t wr * *t wr > t wr (min) dax0 dax1 dax2 dax3 dax4 dax5 dax6 dbx3 dbx4 dbx5 dbx6 dbx7 day0 day1 day2 day3 dax7 dbx2 dbx0 dbx1 a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 51 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 13.1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck1 dsf bank a read and write cycle (burst length = 4, cas latency = 1) rax rax cax cay caz day3 the write data is masked with a zero clock read command bank a write command bank a ax0 ax1 ax2 ax3 day0 day1 az0 az1 az3 latency the read data is masked with a two clock latency read command bank a a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 52 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 13.2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck2 dsf bank a read and write cycle (burst length = 4, cas latency = 2) rax rax cax cay caz the write data is masked with a zero clock read command bank a write command bank a ax0 ax1 ax2 ax3 day0 day1 day3 az0 az1 az3 latency the read data is masked with a two clock latency read command bank a a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 53 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 13.3 read and write cycle (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck3 dsf bank a rax rax cax caz the write data is masked with a zero clock read command bank a write command bank a ax0 ax1 ax2 ax3 day0 day1 day3 az0 az1 az3 latency the read data is masked with a two clock latency read command bank a a9 a0 ~ a8 cke cs ras c as we cay document:1g5-0145 rev.1 page 54 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 14.1 (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck1 dsf bank a interleaving column read cycle rax rax cax cay read command bank b ax0 ax1 ax2 ax3 bw0 bz2 precharge command bank a rbw rbw cbw cbx cby cbz bz1 bw1 bx0 bx1 by0 by1 ay0 ay1 bz0 bz1 bz3 t rcd t ac1 read command bank a activate command bank b read command bank b read command bank b read command bank a read command bank b precharge command bank b a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 55 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 14.2 (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate command hi-z t ck2 dsf bank a interleaving column read cycle rax rax cax read command bank b ax0 ax1 ax2 ax3 bw0 precharge command bank a cbw cbx cay cby cbz bw1 bx0 bx1 by0 by1 ay0 ay1 bz0 bz1 bz3 t rcd t ac2 read command bank a activate command bank b read command bank b read command bank b read command bank a read command bank b precharge command bank b rbw rbw bz2 a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 56 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 14.3. interleaved column read cycle (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk bs dqm dq activate bank a command activate command bank b hi-z read bank a dsf t ck3 rax rbx command t rcd rax read bank b command read bank b command read bank b command precharge bank b command read bank a command precharge bank a command ay3 ax0 ax1 ax2 ax3 bx0 bx1 by0 by1 bz0 bz1 ay0 ay1 ay2 t ac3 cax rbx cbx cby cbz cay a9 a0 ~ a8 cke cs ras c as we document:1g5-0145 rev.1 page 57 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 15.1. interleaved column write cycle (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we bs dqm dq activate bank a command activate command bank b hi-z dsf t ck1 rax cby cbz dax1 dax0 dax2 dax3 dbw1 dbw0 dbx0 dbx1 dby0 day0 day1 dby1 dbz0 dbz3 dbz2 dbz1 t rrd t rcd t rp t wr t rp write bank a command write bank b command precharge command bank a precharge command bank b write bank b command write bank b command write bank a command write bank b command rax rbw cax rbw cbw cbx cay a9 a0 ~ a8 document:1g5-0145 rev.1 page 58 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 15.2. interleaved column write cycle (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 bs a9 dqm a0 ~ a8 dq activate bank a command activate command bank b hi-z dsf write bank a command write bank b command precharge command bank a precharge command bank b write bank b command write bank b command write bank a command write bank b command dax1 dax0 dax2 dax3 dbw1 dbw0 dbx0 dbx1 dby0 day0 day1 dby1 dbz0 dbz3 dbz2 dbz1 t rcd t rrd t wr t rp t rp cbz cby cay cbx cbw rbw cax rax rax rbw t ck2 clk cke cs ras c as we document:1g5-0145 rev.1 page 59 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 15.3. interleaved column write cycle (burst length = 4, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 bs dqm dq activate bank a command activate command bank b hi-z dsf write bank a command write bank b command precharge command bank a precharge command bank b write bank b command write bank b command write bank a command write bank b command t rrd > t rrd(min) rax rbw t ck3 dax1 dax0 dax2 dax3 dbw1 dbw0 dbx0 dbx1 dby0 day0 day1 dby1 dbz0 dbz3 dbz2 dbz1 t rcd t wr t rp cbz cby cay cbx cbw rbw cax rax t wr (min) a9 a0 ~ a8 clk cke cs ras c as we document:1g5-0145 rev.1 page 60 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 16.1. auto precharge after read burst (burst length = 4, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we bs a9 dqm a0~a8 dq activate bank a command activate command bank b hi-z dsf t ck1 by1 ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 by0 bz3 by2 by3 bz0 bz1 bz2 activate command bank b read command bank a read with command bank b auto precharge read with command bank a auto precharge activate command bank b read with command bank b auto precharge read with command bank b auto precharge high rby rbz cbz rby cay cbx cax rax rbz rax cax cby rbx document:1g5-0145 rev.1 page 61 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram bx1 caz t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 16.2 auto precharge after read burst (burst length = 4, cas latency = 2) clk cke cs ras c as dsf bs a9 dqm cax activate bank a command read with command bank a hi-z t ck2 high we rax raz rax rbx rby raz rbx cbx ray rby cby ax0 ax1 ax2 ax3 bx0 bx2 bx3 ay0 ay1 ay2 ay3 by0 by1 by2 az2 by3 az0 az1 activate bank b command read with command bank b auto precharge read with command bank a auto precharge activate bank b command read with command bank b auto precharge activate bank a command read with command bank a auto precharge a0 ~ a8 dq document:1g5-0145 rev.1 page 62 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram rbx t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 16.3 auto precharge after read burst (burst length = 4, cas latency = 3) bs a9 dqm cax a0 ~ a8 activate bank a command activate command bank b read command bank a hi-z t ck3 rax rbx rby rax cbx cay rby cby ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 by2 by1 by0 activate bank b command read with command bank b auto precharge high dsf by3 read with command bank b auto precharge read with command bank a auto precharge clk cke cs ras c as we document:1g5-0145 rev.1 page 63 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 17.1 auto precharge after write burst (burst length = 4, cas latency = 1) bs a9 dqm rax cax a0 ~ a8 dq activate bank a command activate command bank b write with command bank b hi-z write command bank a t ck1 high rax rbx raz rby rbx cbx cay rby cby caz raz dax0 dax1 dax2 dax3 dbx0 dbx1 dbx2 dbx3 day0 day1 day2 day3 dby0 dby1 dby2 dby3 daz0 daz3 daz2 daz1 activate bank b command activate bank a command auto precharge write with command bank a auto precharge write with command bank b auto precharge write with command bank a auto precharge clk cke cs ras c as we dsf document:1g5-0145 rev.1 page 64 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 17.2. auto precharge after write burst (burst length = 4, cas latency = 2) bs a9 dqm a0 ~ a8 write command bank a t ck2 high rax rbx rby raz rax cax cbx cay rby rbx cby raz caz hi-z dax1 dax2 dax3 dbx0 dbx1 dbx2 dbx3 day0 day1 day2 day3 dby0 dby1 dby2 dby3 daz0 daz3 daz2 daz1 dax0 write with command bank a auto precharge activate command bank b write with command bank b auto precharge activate bank a command activate bank b command activate bank a command write with command bank b auto precharge write with command bank a auto precharge clk cke cs ras c as we dq dsf document:1g5-0145 rev.1 page 65 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 17.3. auto precharge after write burst (burst length = 4, cas latency = 3) bs a9 dqm a0 ~ a8 dq t ck3 dsf high rax cax cbx rbx rby cby hi-z dax1 dax2 dax3 dbx0 dbx1 dbx2 dbx3 day0 day1 day2 day3 dby0 dby1 dby2 dby3 dax0 write with command bank a auto precharge activate command bank b write with command bank b auto precharge activate bank a command activate bank b command write with command bank b auto precharge rax rbx rby cay write command bank a clk cke cs ras c as we document:1g5-0145 rev.1 page 66 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 18.1. full page read cycle (burst length = full page, cas latency = 1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 bs dqm dq high hi-z command burst stop read command bank b activate command bank b t ck1 rbx cbx rbx rby rby rax cax rax ax+1 ax+2 ax-2 ax-1 ax+1 bx bx+1 bx+2 bx+3 bx+4 ax bx+5 bx+6 bx+7 ax t rp t rrd activate command bank b activate bank a command read command bank a precharge bank b command full page burst operation does not the burst counter wraps from the highest order page address back to zero during this time interval terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 67 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 18.2. full page read cycle (burst length = full page, cas latency = 2) activate bank a command activate command bank a hi-z read bank a t ck2 high rax rbx rby rax cax rbx cbx rby ax ax+1 ax+2 ax-2 ax-1 ax ax+1 bx bx+1 bx+2 bx+3 bx+4 bx+5 bx+6 command read bank b command precharge burst stop command command bank b activate command bank b the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. t rp bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 68 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 18.3. full page read cycle (burst length = full page, cas latency = 3) activate bank a command activate command bank b hi-z read bank a t ck3 high rax rbx rby ax ax+1 ax+2 ax-2 ax-1 ax ax+1 bx bx+1 bx+2 bx+3 bx+4 bx+5 command precharge burst stop command command bank b activate command bank b the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. t rp rax cax rbx cbx rby read bank b command bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 69 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram rbx t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 19.1 full page write cycle (burst length = full page, cas latency = 1) t ck1 rax rbx rax cax cbx activate bank a command activate command bank b activate command bank b dax dax+1 dbx dbx+1 dbx+2 write command bank b data is ignored high rby dax+1 dax dax+2 dax+3 dax-1 dbx+7 dbx+3 dbx+4 dbx+5 dbx+6 hi-z write command bank a precharge command bank b burst stop command full page burst operation does not terminate when the burst length is satisfied;the burst counter increments and continues bursting beginning with the starting address the burst counter wraps from the highest order page address back to zero during this time interval bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we rby document:1g5-0145 rev.1 page 70 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram dbx+6 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command t ck2 write command rax rax cax rby cbx rby dax dax-1 dax+3 dax+2 dax+1 bank b bank a precharge command bank b activate command bank b high rbx rbx dax dax+1 dbx dbx+1 dbx+2 dbx+3 dbx+4 dbx+5 write command bank b activate command bank a the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied;the burst counter increments and continues bursting beginning with the starting address. burst stop command data is ignored bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we figure 19.2 full page write cycle (burst length = full page, cas latency = 2) document:1g5-0145 rev.1 page 71 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure19.3 full page write cycle (burst length = full page, cas latency = 3) activate command t ck3 write command rax cax bank a bank a activate command bank b high rax rbx cbx rby precharge command bank b rby dax dax-1 dax+3 dax+2 dax+1 dax dax+1 dbx dbx+1 dbx+2 dbx+3 dbx+4 dbx+5 data is ignored activate command bank b burst stop command write command bank b the burst counter wraps from the highest order page addresss back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied;the burst counter inrements and continues bursting beginning with the starting address. hi-z bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we rbx document:1g5-0145 rev.1 page 72 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 20. byte write operation (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we activate command hi-z t ck2 bs bank a ax1 ax0 ax2 write command bank a dsf dqm0 dqm1~3 dq0 - dq7 dq8 - dq31 rax cax cay caz rax day1 az1 az2 ax2 ax1 ax3 az3 day2 day0 day1 day3 az2 az0 az1 read command bank a upper 3 bytes are masked lower byte is masked upper 3 bytes are masked read command bank a lower byte is masked lower byte is masked high a9 a0 ~ a8 document:1g5-0145 rev.1 page 73 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 21. burst read and single write operation (burst length = 4, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we activate command hi-z t ck2 bs bank a dsf dqm0 dqm1~3 dq0 - dq7 dq8 - dq31 read command bank a lower byte is masked lower byte is masked high rax rax cax caw cay caz ax0 ay1 ay3 az0 ax1 ax2 ax3 dqw0 dqx0 ay0 az0 dqw0 ay3 ay2 ax0 ay0 upptr 3 bytes read command bank a single write bank a command single write bank a command single write bank a command cax hi-z ax1 ax2 ax3 a9 a0 ~ a8 is masked document:1g5-0145 rev.1 page 74 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 22. full page burst read and single write operation activate command bank a dqm1~3 dq0 - dq7 dq8 - dq31 read command bank a read command bank a single write bank a command single write bank a command (burst length = full page, cas latency = 3) burst stop command burst stop command t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we t ck3 bs dsf dqm0 high rav rav cav caw cax cay av0 av1 av2 av3 dqw0 dqx0 av0 av1 av2 av3 av0 av1 av2 av3 dqw0 dqx0 av0 av1 av2 av3 a9 a0 ~ a8 document:1g5-0145 rev.1 page 75 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 23. random row read (lnterleaving banks) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 ck1 t high rbu rav rbw rbx rax rby ray rbz raz rbu rau rbv raw cbu rau cau rbv cbv rav cav rbw cbw raw caw rbx rax cbx cax rby ray rbz cby cay raz cbz bu0 au0 bu1 au1 bv0 bw0 bx0 by0 bx1 av0 aw0 ay0 aw1 ax0 bv1 av1 bw1 ax1 by1 ay1 bz0 rp t rp t rp t rp t rp t rp t rp t rp t rp t rp t activate command bank b activate command bank a read bank b with auto precharge read bank a with auto precharge activate command bank b activate command bank a activate command bank b activate command bank a activate command bank b activate command bank a activate command bank a activate command bank b activate command bank a activate command bank b read bank b with auto precharge read bank b with auto precharge read bank b with auto precharge read bank b with auto precharge read bank b with auto precharge read bank a with auto precharge read bank a with auto precharge read bank a with auto precharge read bank a with auto precharge begin auto bank b precharge begin auto bank a precharge begin auto bank b precharge begin auto bank b precharge begin auto bank b precharge begin auto bank b precharge begin auto bank a precharge begin auto bank a precharge begin auto bank a precharge begin auto bank a precharge (burst length = 2, cas latency = 1) bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 76 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 24. full page random column read (burst length = full page, cas latency = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 ck2 t activate command bank b activate command bank a activate command bank b rax rax cax cbx rbx cay cby caz cbz az0 az1 bz0 bx0 by0 bz2 ay0 ax0 bz1 by1 ay1 az2 read command bank a read command bank b read command bank a read command bank b read command bank a read command bank b precharge command bank b (precharge termination) rbx rbw rbw t rp t rcd t rrd bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 77 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 25. full page random column write (burst length = full page, cas latency = 2) t ck2 rax rbx rbw rax cbz caz rbw rbx cax cbx cay cby t rp t wr activate bank a command activate command dbx0 bank b dax0 activate command bank b day0 day1 dby0 dby1 daz0 daz1 daz2 dbz0 dbz1 dbz2 write command bank a precharge write command bank b write command bank a write command bank b write command bank a command bank b (precharge termination) write data is masked write command bank b t rcd t rrd bs dqm dq a9 a0 ~ a8 dsf clk cke cs ras c as we document:1g5-0145 rev.1 page 78 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 26.1. precharge termination of a burst (burst length = full page, cas latency = 1) clk cke cs ras c as we bs dqm dq activate command t ck1 dsf write command rax rax cax ray cay raz ray raz caz t wr t rp t rp dax4 dax3 dax2 dax1 dax0 ay0 ay1 ay2 daz0 daz6 daz7 daz1 daz2 daz3 daz4 daz5 bank a bank a precharge command bank a precharge termination of a write burst. write data is masked. activate command bank a read command bank a precharge command bank a activate command bank a command write bank a precharge termination of a read burst a9 a0 ~ a8 document:1g5-0145 rev.1 page 79 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 figure 26.2. precharge termination of a burst clk cke cs ras c as we bs dqm dq activate command t ck2 dsf write command rax cax ray t wr t rp t rp dax3 dax2 dax1 dax0 ay0 ay1 daz0 daz1 daz2 bank a bank a precharge command bank a precharge termination of a write burst. write data is masked. activate command bank a read command bank a precharge command bank a activate command bank a precharge termination of a read burst (burst length = 8 or full page, cas latency = 2) high raz rax ray cay raz caz t rp ay2 read command bank a precharge command bank a a9 a0 ~ a8 document:1g5-0145 rev.1 page 80 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram figure 26.3 precharge termination of a burst (burst length = 4, 8 or full page, cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras c as we bs dqm dq activate command t ck3 dsf rax cax bank a read command bank a high rax ray raz ray cay raz dax0 dax1 ay0 ay1 ay2 t rp t rp write command bank a precharge command bank a write data is masked precharge termination of a write burst activate command bank a precharge command bank a activate command bank a precharge termination of a write burst t wr a9 a0 ~ a8 document:1g5-0145 rev.1 page 81 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram ordering information part number frequency package packing type vg4616321bq-7 143mhz qfp tray vg4616321bq-7r 143mhz qfp tape & reel vg4616321bq - 6 166mhz qfp tray vg4616321bq - 6r 166mhz qfp tape & reel vg4616321bq - 5 200mhz qfp tray vg4616321bq - 5r 200mhz qfp tape & reel vg4616322bq-7 143mhz qfp tray vg4616322bq-7r 143mhz qfp tape & reel vg4616322bq-6 166mhz qfp tray vg4616322bq-6r 166mhz qfp tape & reel vg4616322bq-5 200mhz qfp tray vg4616322bq-5r 200mhz qfp tape & reel vg4616321bq - 7 ? vg ? 46 ?16321(2) ? b ? q ? 7 ? r ? vis memory product ? synchronous graphic ? sync, 2k self - ref. 512k x 32 sgram.16321 lvttl, 16322 : sstl-3 ? revision ? package type (q : qfp) ? speed (7 : 7ns, 6 : 6ns , 5 : 5ns) ? packing type (r : tape & reel, blank : tray) document:1g5-0145 rev.1 page 82 vis vg4616321b/vg4616322b 262,144x32x2-bit preliminary cmos synchronous graphic ram outline drawing information detail a seating plane e 0.08mm e 100 1 81 80 d1 d a2 0.12mm 31 30 e1 e a1 m detail a typ. b l1 l 50 51 c q a 3. dimension b does not include dambar protrusion. more than 0.08mm. dambar cannot be located on the lead to be wider than the maximum b dimension by 2. dimension d1 & e1 do not include mold protrusion. allowable dambar protrusion shall not cause the 1. controlling dimension : millimeters allowable protrusion is 0.25mm per side. dimension d1 & e1 include mold mismatch. lower radius or the foot. note: 14.15 17.40 20.15 23.40 0.88 0.73 l q l1 0x --- 1.60 ref. 13.85 17.00 19.85 23.00 e e1 d1 e d 14.00 0.65 basic 17.20 23.20 20.00 0.11 2.50 0.22 0.25 --- a2 c b a1 a 2.70 0.15 --- --- --- dim min. nom. millimeters 0.041 0.035 0.029 1.03 7x 0x --- 0.063 ref. 7x 0.557 0.685 0.793 0.921 0.015 0.114 --- 0.134 0.009 0.026 basic 0.545 0.781 0.669 0.906 0.551 0.677 0.913 0.787 0.098 2.90 0.23 0.38 0.004 0.009 --- 3.40 0.010 --- 0.106 0.006 --- --- --- max. max. min. nom. inches |
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